TY  - JOUR
AU  - Liu, Youguo
AU  - Jiang, Qingguo
PY  - 2026
DA  - 2026/07/01
TI  - Embedded Multi-Core Gyro Attitude Data Acquisition System for Aerospace Vehicle Based on ZYNQ Platform
JO  - Aerospace Engineering Communications
T2  - Aerospace Engineering Communications
JF  - Aerospace Engineering Communications
VL  - 1
IS  - 3
SP  - 93
EP  - 99
DO  - 10.62762/AEC.2026.284427
UR  - https://www.icck.org/article/abs/AEC.2026.284427
KW  - ZYNQ SoC
KW  - aerospace inertial measurement
KW  - gyro attitude data acquisition
KW  - Asymmetric Multi-Processing (AMP)
KW  - AXI DMA
KW  - Inter-Processor Communication (IPC)
KW  - spin lock
AB  - Aiming at the interrupt storm performance bottleneck existing in high-speed gyro attitude signal acquisition of aerospace vehicles, an embedded heterogeneous multi-core data acquisition system based on Xilinx ZYNQ-7000 SoC is proposed for inertial measurement unit (IMU) gyro signal sampling. On the hardware layer, a sensor data interface IP conforming to AXI4-Stream protocol is designed in programmable logic (PL) to collect high-frequency gyro original signals, and an AXI DMA controller builds a wideband direct peripheral-DDR transmission channel to realize zero-copy data writing, greatly reducing processor resource occupation under continuous inertial attitude sampling. On the software layer, an AMP dual-core bare-metal parallel framework is deployed in the processing system (PS): the main core undertakes real-time DMA scheduling and hardware interrupt response for gyro sampling streams, while the auxiliary core independently completes attitude data packaging and external communication transmission, thoroughly decoupling high-speed inertial signal acquisition and low-rate data interaction. Meanwhile, an inter-core communication (IPC) mechanism with ultra-low 1.5 $\mu$s delay is constructed based on on-chip memory (OCM) and spinlock algorithm to guarantee multi-core consistency of gyro attitude data. Closed-loop hardware-software joint verification shows that the system supports lossless gyro data transmission at 2 MB/s under 500 kSPS high sampling rate with zero packet loss; the channel inherent noise is measured at 2.4 mV, well within the 5 mV specification threshold, which meets the high real-time and high-precision measurement requirements of aerospace vehicle inertial gyro attitude sensing, and verifies the engineering advantages of this heterogeneous multi-core architecture in aerospace inertial measurement.
SN  - 3071-1967
PB  - Institute of Central Computation and Knowledge
LA  - English
ER  - 

@article{Liu2026Embedded,
  author = {Youguo Liu and Qingguo Jiang},
  title = {Embedded Multi-Core Gyro Attitude Data Acquisition System for Aerospace Vehicle Based on ZYNQ Platform},
  journal = {Aerospace Engineering Communications},
  year = {2026},
  volume = {1},
  number = {3},
  pages = {93-99},
  doi = {10.62762/AEC.2026.284427},
  url = {https://www.icck.org/article/abs/AEC.2026.284427},
  abstract = {Aiming at the interrupt storm performance bottleneck existing in high-speed gyro attitude signal acquisition of aerospace vehicles, an embedded heterogeneous multi-core data acquisition system based on Xilinx ZYNQ-7000 SoC is proposed for inertial measurement unit (IMU) gyro signal sampling. On the hardware layer, a sensor data interface IP conforming to AXI4-Stream protocol is designed in programmable logic (PL) to collect high-frequency gyro original signals, and an AXI DMA controller builds a wideband direct peripheral-DDR transmission channel to realize zero-copy data writing, greatly reducing processor resource occupation under continuous inertial attitude sampling. On the software layer, an AMP dual-core bare-metal parallel framework is deployed in the processing system (PS): the main core undertakes real-time DMA scheduling and hardware interrupt response for gyro sampling streams, while the auxiliary core independently completes attitude data packaging and external communication transmission, thoroughly decoupling high-speed inertial signal acquisition and low-rate data interaction. Meanwhile, an inter-core communication (IPC) mechanism with ultra-low 1.5 \$\mu\$s delay is constructed based on on-chip memory (OCM) and spinlock algorithm to guarantee multi-core consistency of gyro attitude data. Closed-loop hardware-software joint verification shows that the system supports lossless gyro data transmission at 2 MB/s under 500 kSPS high sampling rate with zero packet loss; the channel inherent noise is measured at 2.4 mV, well within the 5 mV specification threshold, which meets the high real-time and high-precision measurement requirements of aerospace vehicle inertial gyro attitude sensing, and verifies the engineering advantages of this heterogeneous multi-core architecture in aerospace inertial measurement.},
  keywords = {ZYNQ SoC, aerospace inertial measurement, gyro attitude data acquisition, Asymmetric Multi-Processing (AMP), AXI DMA, Inter-Processor Communication (IPC), spin lock},
  issn = {3071-1967},
  publisher = {Institute of Central Computation and Knowledge}
}